Read about how a cache works, what kind of cycles a cache uses, common architectures, major components, common organization schemes - and how the Pentium Processor implements cache.

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from Intel Corp.

The purpose of this paper is two fold. The first part gives an overview of cache, while the second part explains how the Pentium Processor implements cache. A simplified model of a cache system will be examined first. The simplified model is expanded to explain: how a cache works, what kind of cycles a cache uses, common architectures, major components, and common organization schemes.

The implementation may differ in actual designs, however the concepts remain the same. This eliminates unnecessary detail and background in hardware design or system dependency. The second part of this paper gives more detail and specifics of how the internal caches work on the Pentium Processor.

An overview of cache
Before I describe a basic cache model, I need to explain what Cache is. Cache is small high speed memory usually Static RAM (SRAM) that contains the most recently accessed pieces of main memory.

Why is this high speed memory necessary or beneficial? In today’s systems, the time it takes to bring an instruction (or piece of data) into the processor is very long when compared to the time to execute the instruction. For example, a typical access time for DRAM is 60ns. A 100 MHz processor can execute most instructions in 1 CLK or 10 ns. Therefore a bottle neck forms at the input to the processor. Cache memory helps by decreasing the time it takes to move information to and from the processor. A typical access time for SRAM is 15 ns. Therefore cache memory allows small portions of main memory to be accessed 3 to 4 times faster than DRAM (main memory).

How can such a small piece of high speed memory improve system performance? The theory that explains this performance is called “Locality of Reference." The concept is that at any given time the processor will be accessing memory in a small or localized region of memory. The cache loads this region allowing the processor to access the memory region faster. How well does this work? In a typical application, the internal 16K-byte cache of a Pentium® processor contains over 90% of the addresses requested by the processor. This means that over 90% of the memory accesses occurs out of the high speed cache.

So now the question, why not replace main memory DRAM with SRAM? The main reason is cost. SRAM is several times more expense than DRAM. Also, SRAM consumes more power and is less dense than DRAM. Now that the reason for cache has been established, let look at a simplified model of a cache system.

Read the rest of this whitepaper: click link, below.

© 2005 Intel Corp.