Multicore Programming : Microprocessor performance has scaled over the last three decades from devices that could perform tens of thousands of instructions per second to tens of billions of instructions per second in today’s products. Our processors have evolved from super-scalar architecture to instruction-level parallelism, where each evolution makes more efficient use of fast single instruction pipeline. Our goal is to continue that scaling, to reach a capability of 10 tera-instructions per second by the year 2015. The obvious question is: How do we get there?

---

Introduction

The demand for increased performance does not diminish, so more efficient ways to deliver that performance must be found.

By Shu-ling Garver and Bob Crepps, Intel Corp.

Microprocessor performance has scaled over the last three decades from devices that could perform tens of thousands of instructions per second to tens of billions of instructions per second in today’s products. Our processors have evolved from super-scalar architecture to instruction-level parallelism, where each evolution makes more efficient use of fast single instruction pipeline. Our goal is to continue that scaling, to reach a capability of 10 tera-instructions per second by the year 2015. The obvious question is: How do we get there?

The answer to that lies in Moore's Law. In parallel with our architecture scaling, our process technology has advanced or scaled at a rate predicted by Moore's Law. If we look ahead to the next decade, we will have the ability to integrate tens of billions of transistors on a single die. The dual-core Intel® Itanium® processor, code-named "Montecito," already uses 1.7 billion transistors.

As mentioned, our architecture has evolved to get the maximum performance from a single pipeline. However, we can make better use of the increasing number of transistors by moving to architectures that use multiple pipelines, or threads, or cores. We call this shift to multiple threads and cores the Era of Tera-scale Computing.