Because of its unique parallel design, Intel Itanium architecture is especially sensitive to the quality of the code it executes. When it runs optimized, well-formed code, it consistently sets performance records, as reported in numerous publications. But give it inefficiently sequenced code, and it will exhibit substantial performance degradation. When poorly designed code traverses the chip's execution pipeline, it can causes bubbles—a term that describes stalls and other undesirable situations in which the processor is not performing useful work. This article discusses common kinds of bubbles and what developers can do to avoid them. To understand this discussion, it's important to quickly review the salient points of Itanium instruction execution.

Itanium 2 microarchitecture highlights
The Itanium 2 processor is a 64-bit processor designed for parallel instruction execution. Under optimal circumstances, it can retire six instructions per clock cycle. Instructions are fed into the pipeline in bundles consisting of up to three instructions each. Instruction scheduling is more important on the Itanium architecture than in RISC and CISC processors, because parallel execution requires careful scheduling of instructions that depend on each other. The complexity of this scheduling places considerable pressure on the compiler to generate an ideal instruction sequence, and constant work is being done to improve the instruction flows both by expanding the capabilities at the silicon level and by refining compiler code generation.

The Itanium 2 processor uses three levels of cache: the innermost (known as level 1 or, simply, L1 ) contains separate 16-KB areas for data and instructions. L2 caches is added, which is fed by a capacious L3 cache. Recent models of the Madison generation of the Itanium processor family sport L3 caches of 6 MB. On CISC processors, such as the Pentium 4 Processor and Intel Xeon Processor families, each level of cache feeds the smaller level below it.