The computing and communication community and industry are stepping up to try to understand the jitter frequency signature in their electrical circuit. They are also exploring advanced circuit and signaling methods to reduce jitter. By reducing the jitter in their platforms, the designers are able to significantly improve the performance goals as measured by bit-error-rate (BER) or speed of the transmitted signal. The circuit enhancements also improve the quality of the signal and reduce overall power consumption.

Conclusion
Low system jitter is the ultimate goal for most, if not all, signal and circuit designers and platform architects. The jitter can be calculated with a software environment that adds jitter from all serial links electrical components. Designers must also enable an optimization method to minimize the noise from the driver, channel, receiver, and clock system.

There are many advanced circuit and signal conditioning methods that are designed to reduce noise from each individual electrical sub blocks. However, the performance optimization of a system as a whole needs extra effort due the additional complexity of jitter measurement as a result of interaction of all serial links elements. This task is not easy, but every signal and circuit designers and system engineers must understand its impact.

Credits
I would like to thank the reviewers for their invaluable comments: Raza Ishfaqur, Chamath Abhayagunawardhana, and Oleg Mikulchenko.

Related links

• Enterprise Developer Center – Intel Software Network
• Pentium® 4 Processor Developer Center – Intel Software Network
• Digital Media Developer Center – Intel Software Network

About the author
Mohammad Kolbehdari is senior staff platform architecture in the Digital Enterprise Group, Intel Corporation. He received Ph.D., M.Sc., and B.Sc. degrees in Electrical Engineering from Temple University, University of Mississippi, Oxford, and Communication University Tehran, in 1994, 1991, and 1986 respectively. He joined Intel in 1998 and has been involved in many products development including the Pentium 4 FSB and PCI Express electrical designs. His areas of interest are signal and circuit integrity, such as EM modeling, power delivery analysis, I/O circuit design, platform architect, system-clock jitter analysis and measurements. Prior to joining Intel, He conducted signal and circuit research in the EM lab at Temple University for one year and joint the Department of Electronics, Carleton University, at Ottawa, Canada as a research associate faculty member from 1994 to 1998.

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© 2005 Intel Corp.