Jitter is one of the biggest challenges in the design of today’s faster computing and communication platforms.

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by Mohammad Kolbehdari, platform architecture senior staff, Digital Enterprise Group, Intel Corp.

Jitter (or phase noise) is one of the biggest challenges to overcome when designing today’s computing and communication platforms. The jitter problem becomes more acute as the industry develops electronic devices that are faster, better, and cheaper. In these systems, jitter is a reliable metric used by designers to evaluate the feasibility of their design goals as systems across generations.

With the increasing complexity of computing and communication platforms, the difficulty of measuring jitter is exponentially increased. This is due to the complex interactions among the electrical components of platforms, which confuses platform designers. Jitter is contributed by all components of the computing and communications platforms.

Platforms and jitter
Typical serial links in a computing and communication platforms consist of the four major electrical components for signaling between two end points. Serial differential links include the driver, which sends the electronic digital signal; the channel, which facilitates the signal propagate through the combined medium of package; PCB and connector; and the transmission-lines traces.

At the other end, the receiver detects the signal and the clock to synchronize the driver and receiver to certain limits. Each one of these components alters the signal waveform. From the time the signal is transmitted by the driver through the channel, and is detected at the receiver end, the signal shape goes through different phases of change. These changes happen as the signal propagates through the different electrical components in the system.

For example, Figure 1 shows the signal shape at the transmitter and the receiver ends. You will notice that the signal at the receiver is not the same as what was transmitted. The changes are because of different types of jitter adding into the signal shape. We at Intel®, and many fellow co-travelers, are trying to find a common and standard method for jitter measurement or simulation. But that is not an easy task.

This is a new and challenging issue with the introduction of platforms with increasing numbers of serial links. The primary metric for platform performance is jitter, and the challenge is its calculation or measurement. The complex nature of jitter (caused by the many electrical devices on a platform) makes the jitter estimation more difficult. Real jitter measurement is far from easy. It needs very complex electrical tools and software developments to enable accurate measurements.

Jitter on platforms can significantly reduce the performance of the signal integrity and power integrity of serial links. It is a critical issue and needs to be understood for improving and enhancing the system components and system designs. The signal and circuit integrity designers need to have a very complex software simulation environment to be able to calculate jitter contributed by each one of the major components in the serial links on the platforms.

Jitter has a mixed nature due to the systematic and randomness of electrical devices. For example, jitter caused by a transmission line layout, called inter-symbol interference (ISI) jitter, is very deterministic in nature. Circuit device’s asymmetry causes a duty cycle distortion that is also the deterministic jitter. Deterministic jitter is the date-dependent and bounded.

Jitter can also be data-independent, which is caused by some inherent circuit device characteristics, such as thermal, shot noise and also other device dependencies, such as power supply voltage and voltage control oscillator (VCO) design. These types of jitter are random and are unbounded. Random jitter has Gaussian distribution, and the value of the jitter is determined from the root mean square (RMS). On the other hand, deterministic jitter is defined by peak-to-peak values.

The total jitter for the system, which is combination of both deterministic and random jitter, cannot be calculated from simple algebraic addition. We have to apply complex mathematical algorithms to calculate the total jitter contributed by the separate components. The system jitter is obtained by converting the RMS data to peak-to-peak and then adding the deterministic jitter component. This complex analysis requires several tools and algorithms including many programming resources. We are trying to develop such a complex environment enabling full jitter capability measurement. Today, we may be able to measure the jitter due to individual electrical components but not the jitter for whole platform components in conjunction with all electrical elements on the platform. Accurate estimation of total jitter on platforms can enable the designers to achieve the electrical requirements such as bit-rate, channel length, losses, and layout requirements. Total jitter can also be used to predict the performance of the platform and allows performance comparisons with the previous generation signaling.

Jitter in a circuit can be improved using advanced circuit and signal devices and different signal conditioning techniques, such as equalization of signal and differential signaling. These methods help balance high frequency losses and the low frequency noise, which also helps in EMI reduction. There are other techniques which may be applied at the receiver end to improve circuit performance, for example—increased receiver sensitivities with feedback decision equalizer or 4-PAM signaling levels rather than the binary signaling.