Functional Overview

The Intel StrataFlash® Wireless Memory (L18) with A/D-Multiplexed I/O device provides read-while-write and read-while-erase capability with density upgrades through 256-Mbit. This device provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage.

Each device density contains one parameter partition and several main partitions. The flash memory array is grouped into multiple 8-Mbit partitions for the 64-Mbit and 128-Mbit devices, and into multiple 16-Mbit partitions for the 256-Mbit device. By dividing the flash memory into partitions, program or erase operations can take place at the same time as read operations.

Although each partition has write, erase and burst read capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in read mode. The device allows burst reads that cross partition boundaries. User application code is responsible for ensuring that burst reads don’t cross into a partition that is programming or erasing.

Upon initial power up or return from reset, the device defaults to asynchronous read mode. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.

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