Performance is a key driver in most DSP applications, but it can be very difficult to get numbers as to exactly what performance can be expected with a given CPU architecture. Specifically, if you are anticipating running DSP algorithms on a GPP architecture like PowerPC it can be very difficult to determine the effects of L1 and L2 cache on the processor throughput. Traditional benchmarks must be looked upon with a great deal of skepticism, since the compiler and library vendors often cook these numbers.

Given that, it is nice to see a realistic analysis using real DSP applications such as a report from Sky Computers that was posted on DSP-FPGA.com. It gives an analysis of several PPC-based chips running a number of algorithms that are of particular interest to DSP heads abd can provide the basis for supporting or refuting a decision to use PPC chips for DSP work.

This is an important question these days. Old-school DSP programmers can be very suspicious of GPP architectures, but those suspicions may be due to a simple lack of understanding. Do the numbers in this report help in these decisions?